#ifndef __CSP_SPI_H__
#define __CSP_SPI_H__

//#include "AC33Mx128.h"

typedef struct {

	CSP_REGISTER_T		SPnTDR_RDR;			// offset = 0x0000, R/W
	CSP_REGISTER_T		SPnCR;				// offset = 0x0004, R/W
	CSP_REGISTER_T		SPnSR;				// offset = 0x0008, R/W
	CSP_REGISTER_T		SPnBR;				// offset = 0x000C, R/W

	CSP_REGISTER_T		SPnEN; 				// offset = 0x0010, R/W
	CSP_REGISTER_T		SPnLR;				// offset = 0x0014, R/W


} CSP_SPI_T;




//==========================================================================
//
//	D E F I N A T I O N S
//
//==========================================================================
#define SPI_MASTER								(1)
#define SPI_SLAVE								(0)


#define SPI_PORTSEL_NORMAL						(0)
#define SPI_PORTSEL_STAR						(1)




//==========================================================================
//
//	S T R U C T U R E S 
//
//==========================================================================

//==========================================================================
//
//			SS_enable				= SSMO
//			SS_auto_manual			= SSMOD
//			SS_polarity				= SSPOL
//			SS_mask					= SSMASK
//
//			msb_lsb_first				= MSBF
//			clock_ploarity				= CPOL
//			clock_phase				= CPHA
//			bit_size					= BITSZ
//
//==========================================================================
#define SPI_SS_ENABLE							(1)
#define SPI_SS_DISABLE							(0)

#define SPI_SS_AUTOMATIC						(1)
#define SPI_SS_MANUAL							(0)

#define SPI_SS_ACTIVE_HIGH						(1)
#define SPI_SS_ACTIVE_LOW						(0)

#define SPI_SS_MASKING							(1)
#define SPI_SS_NOT_MASKING						(0)

#define SPI_MSB_FIRST							(1)
#define SPI_LSB_FIRST							(0)

#define SPI_CPOL_ACTIVE_HIGH					(0)
#define SPI_CPOL_ACTIVE_LOW						(1)

#define SPI_CPHA_FRONT_HALF						(0)
#define SPI_CPHA_REAR_HALF						(1)

#define SPI_BITSIZE_8_BITS						(0)
#define SPI_BITSIZE_9_BITS						(1)
#define SPI_BITSIZE_16_BITS						(2)
#define SPI_BITSIZE_17_BITS						(3)



typedef struct {

	UINT8				SS_enable; 
	UINT8				SS_auto_manual; 
	UINT8				SS_polarity; 
	UINT8				SS_masking;	

	UINT8				msb_lsb_first;				
	UINT8				clock_polarity; 
	UINT8				clock_phase;  
	UINT8				bit_size; 

	UINT32				baudrate; 
	
	UINT32				start_len;
	UINT32				burst_len;
	UINT32				stop_len; 

} SPI_CONFIG; 




//==========================================================================
// 	SPnTDR_RDR
//		
//				@ SP0TDR, SP0RDR = 0x4000_9000
//				@ SP1TDR, SP1RDR = 0x4000_9100
//
//==========================================================================


//==========================================================================
// 	SPnCR
//	
//				@ SP0CR = 0x4000_9004
//				@ SP1CR = 0x4000_9104
//
//==========================================================================
#define SPnCR_TXBC								(0x0001<<20)
#define SPnCR_RXBC								(0x0001<<19)

#define SPnCR_DTXIE								(0x0001<<18)
#define SPnCR_DRXIE								(0x0001<<17)
#define SPnCR_SSCIE								(0x0001<<16)
#define SPnCR_TXIE								(0x0001<<15)
#define SPnCR_RXIE								(0x0001<<14)
#define SPnCR_INTR_MASK							(0x001F<<14)

#define SPnCR_SSMOD								(0x0001<<13)
#define SPnCR_SSOUT								(0x0001<<12)

#define SPnCR_LBE								(0x0001<<11)
#define SPnCR_SSMASK							(0x0001<<10)
#define SPnCR_SSMO								(0x0001<<9)
#define SPnCR_SSPOL								(0x0001<<8)


#define SPnCR_MS								(0x0001<<5)
#define SPnCR_MSBF								(0x0001<<4)

#define SPnCR_CPHA								(0x0001<<3)
#define SPnCR_CPOL								(0x0001<<2)

#define SPnCR_BITSZ_8_BITS						(0x0000<<0)
#define SPnCR_BITSZ_9_BITS						(0x0001<<0)
#define SPnCR_BITSZ_16_BITS						(0x0002<<0)
#define SPnCR_BITSZ_17_BITS						(0x0003<<0)
#define SPnCR_BITSZ_MASK						(0x0003<<0)




//==========================================================================
// 	SPnSR
//	
//				@ SP0SR = 0x4000_9008
//				@ SP1SR = 0x4000_9108
//
//==========================================================================
#define SPnSR_TXDMAF							(0x0001<<9)
#define SPnSR_RXDMAF							(0x0001<<8)

#define SPnSR_SBUSY								(0x0001<<7)
#define SPnSR_SSDET								(0x0001<<6)
#define SPnSR_SSON								(0x0001<<5)
#define SPnSR_OVRF								(0x0001<<4)

#define SPnSR_UDRF								(0x0001<<3)
#define SPnSR_SRDY								(0x0001<<2)
#define SPnSR_TRDY								(0x0001<<1)
#define SPnSR_RRDY								(0x0001<<0)

#define SPnSR_INTR_MASK							(SPnSR_TXDMAF|SPnSR_RXDMAF|SPnSR_SSDET|SPnSR_OVRF|SPnSR_UDRF)




//==========================================================================
// 	SPnBR
//	
//				@ SP0BR = 0x4000_900C
//				@ SP1BR = 0x4000_910C
//
//==========================================================================
#define SPnBR_VAL(n)							((n) & 0x0000FFFF)




//==========================================================================
// 	SPnEN
//	
//				@ SP0EN = 0x4000_9010
//				@ SP1EN = 0x4000_9110
//
//==========================================================================
#define SPnEN_ENABLE							(0x0001<<0)




//==========================================================================
// 	SPnLR
//	
//				@ SP0LR = 0x4000_9014
//				@ SP1LR = 0x4000_9114
//
//==========================================================================
#define SPnLR_SPL_VAL(n)						(((n) & 0x00FF)<<16)
#define SPnLR_SPL_MASK							(0x00FF<<16)

#define SPnLR_BTL_VAL(n)						(((n) & 0x00FF)<<8)
#define SPnLR_BTL_MASK							(0x00FF<<8)

#define SPnLR_STL_VAL(n)						(((n) & 0x00FF)<<0)
#define SPnLR_STL_MASK							(0x00FF<<0)



//==========================================================================
// 
//		M A C R O S
//
//==========================================================================
#define CSP_SPI_GET_SPnRDR(spi)					((spi)->SPnTDR_RDR)
#define CSP_SPI_SET_SPnTDR(spi, val)			((spi)->SPnTDR_RDR = (val))
//-----------------------------------------------------------------------------------------
#define CSP_SPI_GET_SPnCR(spi)					((spi)->SPnCR)
#define CSP_SPI_SET_SPnCR(spi, val)				((spi)->SPnCR = (val))
//-----------------------------------------------------------------------------------------
#define CSP_SPI_GET_SPnSR(spi)					((spi)->SPnSR)
#define CSP_SPI_SET_SPnSR(spi, val)				((spi)->SPnSR = (val))
//-----------------------------------------------------------------------------------------
#define CSP_SPI_GET_SPnBR(spi)					((spi)->SPnBR)
#define CSP_SPI_SET_SPnBR(spi, val)				((spi)->SPnBR = (val))
//-----------------------------------------------------------------------------------------
#define CSP_SPI_GET_SPnEN(spi)					((spi)->SPnEN)
#define CSP_SPI_SET_SPnEN(spi, val)				((spi)->SPnEN = (val))
//-----------------------------------------------------------------------------------------
#define CSP_SPI_GET_SPnLR(spi)					((spi)->SPnLR)
#define CSP_SPI_SET_SPnLR(spi, val)				((spi)->SPnLR = (val))
//-----------------------------------------------------------------------------------------





// SPI
extern CSP_SPI_T			* const			SPI0;
extern CSP_SPI_T			* const			SPI1;




//==========================================================================
// 
//		F U N C T I O N    D E C L A R A T I O N S 
//
//==========================================================================
void CSP_SPI_ConfigureGPIO (CSP_SPI_T * const spi, int master_slave, int port_sel); 
void CSP_SPI_Init (CSP_SPI_T * const spi, int master_slave, SPI_CONFIG * p_config); 
void CSP_SPI_Enable (CSP_SPI_T * const spi); 
void CSP_SPI_Stop (CSP_SPI_T * const spi); 
void CSP_SPI_ConfigureInterrupt (CSP_SPI_T * const spi, UINT32 intr_mask, UINT32 enable); 



#endif 


